Field of the Invention
The present invention relates to integrated circuit devices, cell libraries, cell architectures and electronic design automation tools for integrated circuit devices, including finFET devices.
Description of Related Art
FinFET style transistors have been described in D. Hisamoto et al., IEDM, 1998; and N. Lindert et al., IEEE Electron Device Letters, p. 487, 2001. FinFETs have gained acceptance recently as the requirements of low power and compact layout have become more demanding. In CMOS devices, N-channel and P-channel blocks of transistors are placed in proximity, with insulators in between to prevent latch up, cross-talk and other problems.
In the design of integrated circuits, standard functional cell libraries are often utilized. FinFETs have been implemented in block structures having a grid structure, in which fins are laid out in parallel in first direction on a substrate with a narrow pitch, and gates are laid out in an orthogonal direction across the fins. The individual functional cells are formed using sets of complementary n-channel and p-channel transistors having their source, drain and channel in the fins. To form the functional cells, the fins are sometimes cut in segments to isolate one functional cell from another. This cutting of the fins results in some transistors in the functional cells located on the ends of the fins, and others located inside the fins, away from the ends. Differences in structure that result from location on the fins, can have an effect on the characteristics of the transistors in the functional cells. For example, the stress in the channels of finFET transistors has an impact on transistor performance. So, stressors are used to induce desired levels of stress. However the stress in the channels of the transistors on the ends of fins, i.e. in the locations at which the fins are cut can be different than the stress in the channel of transistors located away from the ends. This variation in transistor performance complicates integrated circuit design.
It is desirable to provide a finFET-based design architecture suitable for implementation of functional cells for a standard functional cell library, and for implementation of integrated circuits using finFET architectures, with flexible layout features while minimizing variations in performance of the transistors.